Algorithm guide · arithmetic
QRAM fan-out toy
Route one address to either of two one-bit cells and read the selected bit coherently.
Circuit size: 5 qubits · 2 cells
CX and controlled SWAP · Addressing memory · Entanglement versus copying
Review quantum fundamentals →Notation used in this lesson
- |ψ⟩ and ⟨ψ|
- A state vector (ket) and its conjugate transpose (bra). ⟨a|b⟩ is their inner product.
- α, β and i
- α and β are complex amplitudes; i²=−1. A probability is the squared magnitude |α|².
- XOR, · and ⊗
- XOR adds bits modulo two. In s·x, multiply corresponding bits and XOR them. ⊗ combines registers or operations on different wires.
- U†, Σ and Tr
- U† is the adjoint (inverse for a unitary). Σ sums terms. Tr is the matrix trace, the sum of diagonal entries.
- Probability, shots and angles
- Ideal probabilities describe the model; measured shot frequencies fluctuate. Angles inside trigonometric expressions are in radians unless explicitly labeled turns.
1. The problem
Read either of two classical one-bit cells into a clean bus, controlled by one address qubit. Preserve both cells and clear routing work. Explore what happens when the address is a superposition.
2. How it works
A routing branch coherently selects which cell interacts with the bus. Reverse the routing afterward so the branch returns to zero. A superposed address gives correlated address/data branches, not two readable cell values in one shot.
Prepare address and cells
Choose address 0,1 or |+⟩ and cell values d0,d1.
Route
Fan out the computational-basis address into a clean branch and use CSWAP routing.
Read
XOR the selected value into the initially zero bus.
Unroute
Reverse the swaps and fan-out, then measure address and bus.
3. The mathematics, one idea at a time
This notation suppresses the unchanged cells and the cleaned routing wire.
When d0≠d1, the address and bus become entangled. CNOT fan-out is not cloning an arbitrary unknown state.
Work this through by hand
4. Two cells containing 0 and 1
Five fixed wires: address, routing branch, two cells and bus. A basis-address warm-up uses the same circuit width.
First try address 0: the bus is 0. Then choose |+⟩ for the worked superposition with cells 0 and 1.
| Stage | Calculation or state | What it means |
|---|---|---|
| Prepare address | (|0⟩+|1⟩)/√2 | Both possible routes have equal amplitude. |
| Read the cells | (|0,0⟩+|1,1⟩)/√2 | Each route carries its own selected data. |
| Uncompute route | Routing branch → |0⟩ | Only the intended address/bus correlation remains. |
Expected outcomes for this example
These are ideal predictions for the stated configuration, not a result already measured by your browser. Rows describing alternative modes or combined events are labeled explicitly.
| Outcome or event | Ideal probability | Interpretation |
|---|---|---|
| 00 | 50% ideal | Address 0 and bus 0. |
| 11 | 50% ideal | Address 1 and bus 1. |
5. Load the worked example in Composer
The worked example can use smaller or simpler inputs than the gallery defaults. The button below loads the exact circuit used in this lesson.
- Address
- |+⟩ · both addresses
- Cell 0
- 0
- Cell 1
- 1
- Save any current circuit you want to keep, then open the worked example. Loading it does not execute a paid hardware job.
- Trace the preparation, main operations and measurements against the worked table. Check the gate editor for controls, targets and angles.
- Start with an ideal noiseless simulator compatible with the circuit. Mid-circuit measurement, reset and feed-forward require support from the chosen backend.
- Inspect the live preview. For a recorded experiment, open Execute, set the available backend options and shots, and Run. Sign in when prompted to retain it in My Jobs.
- Read the output as described below before changing one setting and repeating. The guide describes the original example; edits can change the answer.
6. Read the output correctly
The displayed c1c0 order is address|bus. The examples 00 and 11 look the same either way, so check a basis run: address 0 with cell0=1 produces address|bus=01.
Each shot reveals one pair. Repeating can reveal both pairs; a single read does not expose a whole memory array.
A bit label is a register value; its bar height is a probability or count. For S shots and observed count k, the sampled frequency is k/S. A typical sampling scale for probability p is √[p(1−p)/S]; this is not a strict error bound. Finite samples do not have to match the ideal percentages exactly.
7. Common mistakes & limits
- This is a one-level gate-model toy, not a scalable physical QRAM implementation.
- Equal cell values do not entangle address and bus; both branches then have the same bus state.
8. Check your understanding
If both cells contain 1 and address is |+⟩, what labels occur?
Reveal the reasoning
address|bus is 01 or 11, 50% each. The bus is always 1, independent of the address.
9. Further study
The lesson’s register mappings, supported inputs and loadable example follow Quantket’s implemented circuit. A reference may use different wire names, bit order or resource conventions.
Gallery reference: defaults, definitions & implementation notes
Inputs & default settings
Choose a basis or superposed address and the two cell bits; inspect fan-out, route, read and unroute in Composer.
These are the gallery defaults. The worked example above may override them. Configure the card to change the inputs before loading its editable circuit.
- Address
- Default: + · Choices for the current settings: 0 · first cell; 1 · second cell; |+⟩ · both addresses.
- Cell 0
- Default: 0 · Choices for the current settings: 0; 1.
- Cell 1
- Default: 1 · Choices for the current settings: 0; 1.
Implementation notes
The address is copied into a clean routing branch in the computational basis, used to control a CSWAP, then uncomputed. The selected cell XORs into a blank read bus; both cells remain unchanged. Address |+⟩ produces a coherent superposition of address–data pairs, but measurement returns one pair per shot, not both cell values. This one-level gate toy illustrates fan-out routing and is not a scalable physical QRAM architecture. See Giovannetti, Lloyd and Maccone, arXiv:0807.4994.
Default example: predictions & circuit facts
These values describe the unedited default setup. They are predictions and circuit properties, not measured results from your saved execution.
- Address | read bus
- 00 and 11 (50% each)
- Histogram c1c0
- 00 and 11 (50% each)
- After read
- cells = 0, 1; route = 0
Read your saved result
Check the submitted circuit, measured register and execution settings in Run details. Exact results give computed probabilities; sampled results show frequencies from the recorded shots. Edited circuits and noise can change the expected outcome. The algorithm label records the circuit's origin; it does not certify an edited circuit or a measured result.